Static patterns in makefiles

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Bill Caroselli

Static patterns in makefiles

Post by Bill Caroselli » Mon May 12, 2003 7:57 pm

I'm trying to clean up some makefiles.
I have a number of rules defined that are exactly the same except for
the extension of the "source" files. Can I write a static pattern rule
that looks for a match from a list of available file names?

Suppose I have something like:

OBJ=/tmp/obj
SOURCE_FILES1=$(wildcard *.cc)
SOURCE_FILES2=$(wildcard *.cpp)
OBJS1=$(foreach FILE, $(SOURCE_FILES1), $(OBJ)/$(basename $(FILE) ).o )
OBJS2=$(foreach FILE, $(SOURCE_FILES2), $(OBJ)/$(basename $(FILE) ).o )
$(OBJS1) : $(OBJ)/%.o : %.cc
@-$(CXX) $(CXXFLAGS) -c -o$@ $<
$(OBJS2) : $(OBJ)/%.o : %.cpp
@-$(CXX) $(CXXFLAGS) -c -o$@ $<

Could I rewrite the compile rules into a single rule like:

$(OBJS1) $(OBJS2) : $(OBJ)/%.o : $(filter %.cc %.cpp, $(SOURCE_FILES1) $(SOURCE_FILES2) )
@-$(CXX) $(CXXFLAGS) -c -o$@ $<

P.S.
My actual example is not a compile example & there can be many identicle rules

Guest

Re: Static patterns in makefiles

Post by Guest » Tue May 13, 2003 4:30 pm

Bill Caroselli <qtps@earthlink.net> wrote:
I'm trying to clean up some makefiles.
I have a number of rules defined that are exactly the same except for
the extension of the "source" files. Can I write a static pattern rule
that looks for a match from a list of available file names?
...
Could I rewrite the compile rules into a single rule like:

$(OBJS1) $(OBJS2) : $(OBJ)/%.o : $(filter %.cc %.cpp, $(SOURCE_FILES1) $(SOURCE_FILES2) )
@-$(CXX) $(CXXFLAGS) -c -o$@ $
Sorry, it doesn't look like it. Pattern rules act like normal ones,
so you'd be declaring multiple pre-requisites for the object file(s).


--
Brian Stecher (bstecher@qnx.com) QNX Software Systems, Ltd.
phone: +1 (613) 591-0931 (voice) 175 Terence Matthews Cr.
+1 (613) 591-3579 (fax) Kanata, Ontario, Canada K2M 1W8

Bill Caroselli

Re: Static patterns in makefiles

Post by Bill Caroselli » Tue May 13, 2003 5:24 pm

bstecher@qnx.com wrote:
bqc > Bill Caroselli <qtps@earthlink.net> wrote:
I'm trying to clean up some makefiles.
I have a number of rules defined that are exactly the same except for
the extension of the "source" files. Can I write a static pattern rule
that looks for a match from a list of available file names?
bqc > ...
Could I rewrite the compile rules into a single rule like:

$(OBJS1) $(OBJS2) : $(OBJ)/%.o : $(filter %.cc %.cpp, $(SOURCE_FILES1) $(SOURCE_FILES2) )
@-$(CXX) $(CXXFLAGS) -c -o$@ $
bqc > Sorry, it doesn't look like it. Pattern rules act like normal ones,
bqc > so you'd be declaring multiple pre-requisites for the object file(s).

Yes. I discovered this. Then I guess thjere is no other way to do it?

Guest

Re: Static patterns in makefiles

Post by Guest » Tue May 13, 2003 7:03 pm

Bill Caroselli <qtps@earthlink.net> wrote:
bstecher@qnx.com wrote:
bqc > Sorry, it doesn't look like it. Pattern rules act like normal ones,
bqc > so you'd be declaring multiple pre-requisites for the object file(s).

Yes. I discovered this. Then I guess thjere is no other way to do it?
Not that I can think of.

--
Brian Stecher (bstecher@qnx.com) QNX Software Systems, Ltd.
phone: +1 (613) 591-0931 (voice) 175 Terence Matthews Cr.
+1 (613) 591-3579 (fax) Kanata, Ontario, Canada K2M 1W8

Bill Caroselli

Re: Static patterns in makefiles

Post by Bill Caroselli » Thu Oct 30, 2003 4:46 pm

I have a new static patterns question.

Given:

LIST := file1.x dir/file2.x file3.x
$(LIST) : %.x : %.y

I would like the dependancy pattern to not include the directory part
of the target. I.E.
file1.x depends on file1.y
dir/file2.x depends on file2.y
file3.x depends on file3.y

I tried something screwy like:
$(LIST) : %.x : $(notdir %).y

but this did not work.

The LIST is very long and dynamically built so I can't just hard code
what I need. Can this be done?

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